Recently, with the an improvement of CPU functions, systems having a wide data bus or buses have been used more and more. Accordingly, the memory elements with data buses as wide as several bytes have been required. In addition, a read/write function in unit of byte has been also required for the memory elements.
FIG. 5 is a system diagram showing a conventional asynchronous semiconductor memory device having a two-byte data width, in which the data are handled as upper byte data and lower byte data.
In the input/output data, the upper byte data thereof are inputted and/or outputted through data input/output terminals I/OUB1 to I/OUB8 (referred to as I/OUBm, hereinafter). On the other hand, the lower byte data are inputted and/or outputted through data input/output terminals I/OLB1 to I/0LB8 (referred to as I/OLBn, hereinafter).
In the upper byte write operation, the data inputted through the data input/output terminals I/OUBm are outputted to an upper byte internal data bus DbusUB via upper byte data input buffers Din UBm. On the other hand, in the upper byte read operation, the data on the upper byte internal data bus DbusUB are outputted through the data input/output terminals I/OUBm via upper byte data output buffers DoutUBm.
In the lower byte write operation, the data inputted to the data input/output terminals I/OLBn are outputted to a lower byte internal data bus DbusLB via lower byte data input buffers DinLBm. On the other hand, in the lower byte read operation, the data on the lower byte internal data bus DbusLB are outputted through the data input/output terminals I/OLBn via lower byte data output buffers DoutLBn.
The upper byte data input buffers DinUBm and the upper byte data output buffers DoutUBm are connected to the internal data bus DbusUB. The upper byte data input buffers DinUBm are controlled by an upper byte write request signal WEUB. Further, the data inputted to the upper byte data input buffers DinUBm are outputted to the internal data bus DbusUB, except a stand-by status for power saving.
The lower byte data input buffers DinLBn and the lower byte data output buffers DoutLBn are connected to the internal data bus DbusLB. The lower byte data input buffers DinLBn are controlled by a lower byte write request signal WELB. Further, the data inputted to the lower byte data input buffers DinLBn are outputted to the internal bus DbusLB, except a stand-by status for power saving.
The memory element as shown in FIG. 5 is controlled on the basis of an upper byte control signal /UB, a lower byte control signal /LB and a write request signal /WE all applied externally. The upper byte control signal /UB is inputted via an upper byte control signal buffer UBbuffer. The lower byte control signal /LB is inputted via a lower byte control signal buffer LBbuffer. The write request signal /WE is inputted to the upper byte control signal buffer UBbuffer, the lower byte control signal buffer LBbuffer, and a write request signal detecting section WEdet.
The upper byte control signal buffer UBbuffer supplies upper byte write request signals WEUB and /WEUB to an internal memory. The lower byte control signal buffer LBbuffer supplies lower byte write request signals WELB and /WELB to the internal memory.
The write request signal detecting section WEdet supplies a write start synchronous pulse .phi.WS and a write end synchronous pulse .phi.WE to the internal memory.
The upper byte data input buffers DinUBm and the lower byte data input buffers DinLBn are activated on the basis of the upper byte write request signals WEUB and /WEUB and the lower byte write request signals WELB and /WELB. A data transition detecting circuit DTD monitors the statuses of data inputted to the upper byte data input buffers DinUBm and the lower byte data input buffers DinLBn through the data input/output terminals I/OUBm and I/OLBn, respectively. When the data inputted to the upper byte data input buffers DinUBm and the lower byte data input buffers DinLBn through the data input/output terminals I/OUBm and I/OLBn change, the data transition detecting circuit DTD detects the changes and then outputs a data transition pulse .phi.DTD.
An address transition pulse .phi.ATD of an address transition detecting circuit ATD, the data transition pulse .phi.DTD of the data transition detecting circuit DTD, the write start synchronous pulse .phi.WS and the write end synchronous pulse .phi.WE of the write request signal detecting section WEdet are all inputted to an automatic power-down circuit APDbuffer. The automatic power-down circuit APDbuffer supplies an automatic power-down signal APD to the internal memory. When the statuses of data inputted to the upper byte data input buffers DinUBm and the lower byte data input buffers DinLBn through the data input/output terminals I/OUBm and I/OLBn do not change, after a predetermined time has elapsed, this power-down circuit APDbuffer reduces the power automatically, under control of the write start synchronous pulse WS and the data transition pulse .phi.DTD, for power saving of the memory chip. On the other hand, an address transition pulse .phi.ATD of an address transition detecting circuit ATD and the write end synchronous pulse .phi.WE of the write request signal detecting section WEdet are inputted to an equalizer circuit EQbuffer. The equalizer circuit EQbuffer supplies an equalize/pull-up pulse .phi.Eq to data lines in the memory device. The pulse .phi./Eq is supplied to gates of equalize transistors TUBEq and TLBEq for equalizing upper and lower byte data lines dUB, /dUB and dLB, /dLB.
In a section S designated by a memory address signal As, select cells ZUB corresponding to the upper byte and select cells ZLB corresponding to the lower byte are arranged. One of the two upper and lower byte select cells ZUB and ZLB can be selected by activating a word line WL.
The select cells ZUB are connected to the upper byte data lines dUB and/dUB via gates G controlled by column decode lines CD. On the other hand, the select cells ZLB are connected to the lower byte data lines dLB and/dLB via the gates G controlled by the column decode lines CD.
On the other hand, the upper byte data lines dUB and dUB are connected to a section write buffer SWBUB and a section read buffer SSAUB for transferring data to and from the internal data bus DbusUB. Further, the section write buffer SWUB and the section read buffer SSAUB are controlled on the basis of the upper byte write request signal WEUB and the automatic power-down signal APD, and the address signal As.
Further, the lower byte data lines dLB and/dLB are connected to a section write buffer SWLB and a section read buffer SSALB for transferring data to and from the internal data bus DbusLB. Further, the section write buffer SWBLB and the section read buffer SSALB are controlled on the basis of the lower byte write request signal WELB and the automatic power-down signal APD and the address signal As.
When the automatic power-down signal APD is at "L" level, the memory cells sets the section write buffer SWBUB and the section write buffer SWBLB to a stand-by status, respectively. Further, when there exists a change in data inputted to the upper byte data input buffers DinUBm and the lower byte data input buffers DinLBn through the data input/output terminals I/OUB and I/OLB, and thereby when the data transition detecting circuit DTD detects data change, the automatic power-down buffer APD buffer changes the automatic power-down signal from the "L" level to the "H" level by releasing the automatic power-down operation.
The operation of the memory device constructed as described above will be described hereinbelow with reference to the timing charts shown in FIG. 6. In FIG. 6, /WE denotes the write request signal /WE; /UB denotes the upper byte control signal /UB; /LB denotes the lower byte control signal /LB; WEUB denotes the upper byte write request signal WEUB; WELB denotes the lower byte write request signal WELB; /WEUB denotes the upper byte write request signal /WEUB; /WELB denotes the lower byte write request signal /WELB; .phi.WS denotes the write start synchronous pulse .phi.WS; I/OUBM denotes the status of the data input/output terminal I/OUBm; I/OLBn denotes the status of the data input/output terminal I/OLBn; .phi.DTD denotes the data transition pulse .phi.DTD; APD denotes the automatic power-down signal APD; DBusUB denotes the status of the internal data bus DbusUB; DBusLB denotes the states of the internal data bus DbusLB; DUB//dUB denotes the upper byte data lines dUB and /dUB; and dLB//dLB denotes the lower byte data lines dLB and /dLB.
First, at time t0, the assumption is made that the status of data applied to the data input/output terminals I/OUBm and the data input/output I/OLBn changes and further the write request signal /WE changes from the "H" level to the "L" level.
As a result, in response to the change of the write request signal /WE, the write request signal detecting section WEdet outputs the "H"-level write start synchronous pulse .phi.WS for a predetermined time beginning at time t2.
On the other hand, at time t1 after time t0, the upper byte control signal /UB and the lower byte control signal /LB change from the "H" level to the "L" level.
As a result, in response to the changes of the upper byte control signal /UB and the write request signal /WE, the upper byte control buffer UBbuffer changes the upper byte write request signal WEUB from the "L" level to the "H" level at time t3 and the upper byte write request signal /WEUB from the "H" level to the "L" level also at time t3.
On the other hand, in response to the changes of the lower byte control signal /LB and the write request signal /WE, the lower byte control buffer LBbuffer changes the lower byte write request signal WELB from the "L" level to the "H" level at time t3 and the lower byte write request signal /WELB from the "H" level to the "L" level also at time t3.
As a result, in response to the upper byte write request signal /WEUB, the upper byte data input buffers DinUBm inputs the data applied through the data input/output terminals I/OUBm, and simultaneously outputs the inputted data to the upper byte internal data bus DbusUB at time t5 in response to the upper byte write request signal WEUB.
On the other hand, in response to the lower byte write request signal /WELB, the lower byte data input buffers DinLBm inputs the data applied through the data input/output terminals I/OLBm, and simultaneously outputs the inputted data to the lower byte internal data bus DbusLB at time t5 in response to the lower byte write request signal WELB.
Further, in response to the changes of data inputted to the upper byte data input buffers DinUBm and the lower byte data input buffers DinLBn, the data transition detecting circuit .phi.DTD outputs the "H" level data transition pulse .phi.DTD for a predetermined time beginning at time t4.
On the other hand, on the basis of any one of the data transition pulse .phi.DTD from the data transition detecting circuit DTD and write start synchronous pulse .phi.WS from the write request signal detecting section WEdet, the automatic power-down circuit APDbuffer keeps the automatic power-down signal APD at the "H" level for a predetermined time between time t6 and time t8 to keep the device activated until the write operation ends.
In response to a series of the above-mentioned operation, the automatic power-down of the section S selected by the address signal As is released. Further, through the section write buffer SWBUB of the section S activated by the upper byte write request signal WEUB, the statuses of the upper byte internal data bus DbusUB are given to the upper byte data lines dUB and /dUB at time t7. As a result, the statuses of the upper byte data lines dUB and /dUB are written in the selected memory cells ZUB via the gate G controlled by the column decode lines CD.
On the other hand, the automatic power-down of the section S selected by the address signal As is released. Further, through the section write buffer SWBLB of the section S activated by the lower byte write request signal WELB, the statuses of the lower byte internal data bus DbusLB are given to the lower byte data lines dLB and /dLB at time t7. As a result, the statuses of the lower byte data lines dLB and/dLB are written in the selected memory cells ZLB via the gate G controlled by the column decode lines CD.
After that, at time t9, when data inputted through the data input/output terminals I/OLBn change, new data are outputted to the lower byte internal data bus DbusLB via the lower byte data input buffers DinLBn. Simultaneously, in response to the change of the data inputted to the lower byte data input buffers DinLBn, the data transition detecting circuit DTD outputs the "H" level data transition pulse .phi.DTD for a predetermined time beginning at time t10. In response to the data transition pulse .phi.DTD, the automatic power-down circuit APDbuffer already set to the automatic power-down status keeps again the automatic power-down signal APD at the "H" level for a predetermined time between time t12 and time t16. On the basis of these operation, the automatic power-down of the section S selected by the address signal As is released. Further, through the section write buffer SWBLB of the section S activated by the lower byte write request signal WELB, the new data on the lower byte internal data bus DbusLB are given to the lower byte data lines dLB and /dLB at time t13. As a result, the statuses of the lower byte data lines dLB and /dLB are written in the selected memory cells ZLB via the gate G controlled by the column decode lines CD.
Further, when the upper byte control signal /UB is set to non-selection at time t14, the upper byte write request signal WEUB changes to the "L" level at time t15, and the upper byte write request signal /WEUB changes to the "H" level at time t15, so that both the signals are disabled. As a result, the section write buffer SWBUB changes to the stand-by status. At the same time, the operation of the initial stage is disabled by the upper byte write request signal /WEUB for prevention of current from passing through the initial stage of the upper byte data input buffers DinUBm. Further, the output statuses of the upper byte data input buffers DinUBm are set to a high impedance for protection of the data on the upper byte internal data bus DbusUB.
On the other hand, when the lower byte control signal /LB is set to non-selection at time t14, the lower byte write request signal WELB changes to the "L" level at time t15, and the lower byte write request signal /WELB changes to the "H" level at time t15, so that both the signals are disabled. As a result, the section write buffer SWBLB changes to the stand-by status. At the same time, the operation of the initial stage is disabled by the lower byte write request signal /WELB for prevention of current from passing through the initial stage of the lower byte data input buffers DinLBm. Further, the output statuses of the lower byte data input buffers DinLBm are set to a high impedance for protection of the data on the lower byte internal data bus DbusLB.
As described above, whenever the data are written in unit of byte, the upper byte control signal /UB and the lower byte control signal /LB both change independently in the same write cycle.
FIG. 7 shows an initial stage of the lower byte data input buffers DinLBn connected to the data input/output terminal I/OLBn. In the drawing, data inputted through the data input/output terminal I/OLBn is given to a NOR type gate NOR to which the lower byte write request signal /WELB is inputted.
In the circuit as shown in FIG. 5, the operation obtained when only the lower byte control signal /LB changes freely will be described hereinbelow with reference to a timing chart shown in FIG. 8. In FIG. 8, /WE denotes the write request signal /WE; /LB denotes the lower byte control signal /LB; WELB denotes an inversion signal WELB of the lower byte write request signal /WELB; /WELB denotes the lower byte write request signal /WELB; I/OLBn denotes the status of the data input/output terminals I/OLBn; .phi.WS denotes the write start synchronous pulse .phi.WS; .phi.DTD denotes the data transition pulse .phi.DTD; APD denotes the automatic power-down signal APD; DbusLB denotes the status of the internal data bus DbusLB; and dLB//dLBn denotes the lower byte data lines dLB and /dLB.
The operation obtained when the status of data inputted through the data input/output terminals I/OLBn changes at time t0 and thereby the write request signal /WE changes from the "H" level to the "L" level and after that the lower byte control signal /LB changes from the "H" level to the "L" level at time t1 is quite the same as before.
That is, when the write request signal /WE and the lower byte control signal /LB change from the "H" level to the "L" level, the lower byte write request signal WELB changes from the "H" level to the "L" level at time t2 and simultaneously the lower byte write request signal /WELB changes from the "L" level to the "H" level. As a result, through the NOR type gate NOR to which the lower byte write request signal /WELB is inputted, the data inputted through the data input/output terminal I/OLBn is inputted to the lower byte data input buffers DinLBn. At the same time, on the basis of the changed lower byte write request signal WELB, the output of the lower byte data input buffer DinLBn is set to a high impedance status. In other words, the input data status of the data input/output terminal I/OLBn is outputted to the lower byte internal data bus DbusLB at time t5.
On the other hand, in response to the change of the write request signal /WE, the write request signal detecting section WEdet outputs the "H" level write start synchronous pulse .phi.WS for a predetermined time beginning at time t3. In the same way, in response to the change of data inputted to the lower byte data input buffers DinLBn, the data transition detecting circuit DTD outputs the "H" level data transition pulse .phi.DTD for a predetermined time beginning at time t4. In response to this, the automatic power-down circuit APDbuffer keeps the automatic power-down signal APD at the "H" level for a predetermined time between time t6 and time t9, to maintain the device operation until the write operation ends.
As a result, at time t6, data are outputted from the lower byte data input buffers DinLBn to the internal data bus DbusLB, so that the data inputted to the data input/output put/out terminals I/OLBn are written in the selected cells ZLB in the same process as described before.
However, when the lower byte control signal /LB returns to the "H" level at time t8, the lower byte write request signals WELB and /WELB return to the "L" and "H" levels, respectively by following up the "H" level lower byte control signal /LB.
Here, the assumption is made that the automatic power-down signal APD returns from the "H" level to the "L" level into the automatic power-down mode again at time t10, and further the data inputted to the data input/output terminals I/OLBn are all set to the "H" level at time t11.
Under these conditions, when the write request signal /WE is at the "L" level and further the lower byte control signal /LB changes from the "H" level to the "L" level at time 12, the lower byte write request signals WELB and /WELB of the lower byte control buffer LBbuffer change to the "H" level and the "L" level, respectively at time t13.
As a result, the data inputted through the lower byte data input/output terminals I/OLBn are transmitted to the lower byte data input buffers DinLBn. However, as already explained, since the data inputted through the data input/output terminals I/OLBn are all at the "H" level, the internal statuses of the lower byte data input buffers DinLBn will not change, irrespective of the change of the lower byte write request signal /WELB. Therefore, the data transition detecting circuit DTD cannot generate the data transition pulse .phi.DTD, so that it is impossible to release the automatic power-down status. In other words, it is impossible to write data, irrespective of that the lower byte control signal /LB is being enabled.
On the other hand, another timing chart as shown in FIG. 9 should be noted. In FIG. 9, /WE denotes the write request signal /WE; /LB denotes the lower byte control signal /LB; /UB denotes the upper byte control signal /UB; .phi.WS denotes the write start synchronous pulse .phi.WS; .phi.WE denotes the write end synchronous pulse .phi.WE; APD denotes the automatic power-down signal APD; .phi./Eq denotes the equalize pulse .phi./Eq; DbusUBm denotes status of upper byte internal data bus DbusUBm; and DbusLBn denotes the lower byte internal data bus DbusLBn.
Now, the assumption is made that the data inputted to the data input/output terminals I/OUB and I/OLB change and thereby the write request signal /WE changes from the "H" level to the "L" level at time t0; the upper byte control signal /UB and the lower byte control signal /LB change from the "H" level to the "L" level at time t2; and the address input does not change at all before and after the times t0 and t2.
In this case, as already explained, since the write request signal detecting section WEdet outputs the write start synchronous pulse .phi.WS at time t2, in response to this pulse .phi.WS the automatic power-down circuit APDbuffer changes the automatic power-down signal APD from the "L" level to the "H" level at time t3 to release the power-down.
As a result, the input data are transmitted to the internal data buses DbusUB, and DbusLB to write data in the memory.
On the other hand, when the upper byte control signal /UB changed from the "L" level to the "H" level at time t5; the lower byte control signal /LB changed from the "L" level to the "H" level at time t6; and the automatic power-down signal APD changed from the "H" level to the "L" level at time t7, the device enters into the power-down mode.
Under these conditions, the write request signal /WE is changed from the "L" level to the "H" level at time t8, and further the upper byte control signal /UB and the lower byte control signal /LB are both changed from the "H" level to the "L" level at time t10, to change the write mode to the read mode of the memory.
In this case, write request signal detecting section WEdet outputs the write end synchronous pulse .phi.WE at time t11. Therefore, at time t10, the automatic power-down signal APD changes from the "L" level to the "H" level to release the power-down. At the same time, the equalizer circuit EQbuffer generates the equalize pulse .phi./Eq to equalize/pull-up the data lines and the bus lines in the memory. On the basis of the signal APD and the pulse .phi./Eq, the memory device operates in the same as in the ordinary address access read mode. Therefore, the address access time tACC is equal to the time between when the write request signal /WE changes and when data are outputted to the data input/output terminals I/OUBm and data input/output terminals I/OLBn.
On the other hand, the time between when the upper byte control signal /UB or the lower byte control signal /LB changes into the enable status and when data are outputted to the data input/output terminals I/OUBm or data input/output terminals I/OLBn is defined by the byte access time tUB or tLB. The byte access time tUB or tLB is the time required for outputting the read data (on the upper byte internal data bus DbusUB or the lower byte internal data bus DbusLB), to the data input/output terminals I/OUBm or the data input/output terminals I/OLBn (via the upper byte data output buffers DoutUBm or the lower byte output buffers DoutLBn), which is of course shorter than the address access time tACC. However, in the case of the byte access immediately after the write operation ends as shown in FIG. 9, it is impossible to assure the byte access times tUB or tLB, in spite of the fact that the address does not change. In other words, in FIG. 9, if t10-t8&lt;tACC-tUB=tACC-tLB, a contradiction occurs with respect to the byte access time tUB or tLB. Therefore, a specific specification must be prepared for the countermeasures. However, this is impossible in practice.
In the conventional semiconductor memory device as described above, when data are required to be written in any required byte of a plurality of bytes, it is impossible to write data appropriately according to the data combination status, so that specific countermeasures are inevitably needed. Further, when the written data are required to be read as they are without changing the address, there exists a problem in that a contradiction occurs in the output data specification.